Parity Control in the Magtape IO Processor

This technical memorandum from January 19, 1968, details the implementation of parity control for the PDP-X Magtape Processor/TU-XX system to ensure compatibility with IBM equipment. It covers the requirements for generating parity for 9-track operation, including the handling of 9-bit data output and Cyclic Redundancy Character (CRC) computation.

The document describes the necessary hardware modifications to the Control Memory to facilitate parity insertion, specifically defining three new signals: Input Parity Insert, True Parity Insert, and Complemented Parity Insert. The memorandum includes microcode examples and a truth table to demonstrate how these operations allow for the generation and verification of even or odd parity as specified by the system's command word.