Memory Bus Description

This document is a technical memorandum from January 1968 describing the memory bus for the PDP-X computer system. The memory bus facilitates interconnections between a processor (or high-speed I/O device) and memory modules using an interlocked signal system.

Key aspects of the system described include:

• System Organization: The architecture utilizes processors, memory modules, and an optional "arbiter." The arbiter allows for multiprocessor systems by multiplexing memory access ports and managing connections to memory beyond the local configuration.
• Bus Operation: Memory requests are examined by modules; if a local memory does not respond, the arbiter forwards the request to the common memory system. The bus supports specific sequences for Read, Write, and Pause operations, including handshaking signals like REQ, ADDR ACK, and MRLS.
• Parity: Parity is implemented via a parity control unit that checks incoming/outgoing data, which adds a slight delay to memory cycles.
• Hold and Priority: A HOLD line is available to provide high-speed service (over 300,000 words per second) for devices requiring dedicated access or block transfers, overriding standard alternating priority.
• Technical Details: The document includes a table of bus signals (DATA, CON, REQ, etc.) and diagrams illustrating various configurations and signal flow timing for different operation types.