KL10 Student Guide

This student guide covers the architecture and operation of the KL10 CPU, with specific emphasis on the M Box (memory interface, cache memory, paging) and the DTE-20 (PDP-11 console processor interface). It includes detailed descriptions of:

• M Box Architecture: Functions, data flow, cache memory operation (read/write), address modification and verification, and channel control.
• DTE-20 Interface: Programming overview, doorbell function, byte transfer operations, diagnostic features, and communication between the PDP-11 and the KL10 system.
• Paging: Functional descriptions of the pager, KI vs. KL paging modes, address space management, and page table structures.
• System Clocks: Interval timer, time base, performance counters, and accounting meters.

The document is heavily supplemented with block diagrams, microcode flowcharts, and bit-level field descriptions for the control RAM (CRAM) and dispatch RAM (DRAM).