KA11

This manual serves as a comprehensive technical guide for the KA11 Processor, which is the central processing unit for the PDP-11 computer. The documentation is organized into five primary sections:

• Block Diagrams: Provides an overview of the processor structure, including data flow, machine state flow, and connectivity to the Unibus.
• The Instruction Set: Describes the processor's operations using Instruction Set Processor (ISP) notation, detailing data manipulation, addressing modes, and instruction execution processes.
• Machine State Flow Charts: Details the sequence of processor states (Fetch, Source, Destination, Execute, Service) and their underlying logic.
• KA11 Processor Logic Description: Offers a module-by-module breakdown of the processor's hardware implementation, including detailed logic discussions for the timing, registers, data paths, and control signals.
• Maintenance: Includes procedures for system installation, clock adjustment, use of the KM11 Maintenance Set, and diagnostic tips.

The document includes extensive schematic references and wire tables to facilitate hardware troubleshooting and system-level repairs.