PDP-11 Architecture

This interoffice memorandum, dated March 4, 1969, by Rick Merrill, details the proposed architecture and design considerations for the new PDP-11 computer. The document covers several key areas:

• Architecture & Instruction Set: Highlights the conservative yet efficient 8/16-bit design, emphasizing I/O efficiency, cost-effective memory usage, and the ease of programming and debugging.
• Assembler & Mnemonic Design: Discusses the need for a new assembler mnemonic structure, suggesting four-to-six letter mnemonics to facilitate easier coding and byte computation.
• FOCAL-11: Recommends translating the FOCAL interpreter to the PDP-11, estimating significant byte savings compared to the PDP-8.
• Functional Enhancements: Proposes specific hardware features, including a swap instruction, a halt instruction, improved overflow flags, and a more robust implementation of index registers.
• Addressing Modes: Details a proposed method for handling indexed instructions and table operations to maximize bit efficiency.

The document includes a technical mnemonic matrix and details on machine organization, register usage, and addressing modes.