PDP-11 Electrical Design Review

This interoffice memorandum records the proceedings of the second PDP-11 Electrical Design Review meeting held on February 24, 1969. Key discussions included:

• Addressing Scheme: Review of proposed changes and concerns regarding the accessibility of major registers for register-to-register operations.
• Instruction Set: Suggestions for new register-to-register instructions, the utility of auto-increment in memory, and the behavior of the 'load byte' instruction.
• Mnemonics: Standardization of 'inclusive' and 'jump to subroutine' (JSR/JMS) mnemonics to differentiate the PDP-11 from other DEC machines.
• System Design: Discussions on break-point jump facilities, potential removal of increment/decrement AC instructions, the addition of a 'multiply step' instruction, and resolving naming conflicts between register N and condition code bit N.
• Future Topics: Plans for the next meeting focused on architecture, instruction sets, and I/O philosophy.