PDP-11 I/O Bus

This interoffice memorandum, dated 18 April 1969, contains critique and suggestions regarding the PDP-11 I/O bus design from Jerry Butler. The document argues that the current DC interlock bus scheme is relatively slow and fails to achieve total interlock, which may limit the system's performance on larger configurations in the future. The author suggests looking at the design of the PDP-10 memory bus for high-speed alternatives and recommends further investigation into memory cycle times and multiple bus configurations for larger systems. The memorandum includes detailed flow charts illustrating various bus transfer scenarios—priority bus transfers, data-in transfers, data-out transfers, and data-modify transfers—to support the analysis.