Tentative Design Goals for 11/20 Successors

This document is an internal memorandum dated October 22, 1969, from Bruce Delagi to the PDP-11 Steering Committee regarding design goals for processors following the PDP-11/20. It lists 38 potential design goals and features, including memory management, bus operations, parity checking, arithmetic instructions, and paging for time-sharing environments. The author solicits feedback on segmenting these goals for different price-point markets ($13K to $75K).