KAll Design Critique

This document is a technical memorandum from Jim O'Loughlin at Digital Equipment Corporation regarding the design status of the KAll processor. Written in October 1969 as the machine entered the prototype stage, the author provides a critique and recommendations for potential improvements in a future redesign or new processor. The critique covers several key areas:

• Data Paths: Suggests replacing latches with edge-triggered storage, using faster quad adders, and allowing internal memory read/write within a single cycle.
• Memory: Mentions the memory design is satisfactory but notes a lack of memory inhibit for expansion beyond 16 words.
• Bus Interface: Highlights complexity in bus operation and suggests potential improvements for pulse circuits, timing, and bus cycle management.
• General Timing: Discusses clock skew, console timing, and potential optimizations using shift registers.
• Printed Circuits: Notes issues with current layout constraints and IC density requirements.