DMA20 Memory Bus Adapter

This document describes the DMA20 Memory Bus Adapter, which acts as the interface control element between the MBox of the central processor and the external core memory in a KL10 system. It covers the functional structure, operational modes (1-bus, 2-bus, and 4-bus), clocking logic, diagnostic capabilities, error detection and reporting (including parity and NXM checks), and physical configuration. Detailed logic descriptions for cycle operations like read/restore, clear/write, and read/modify/write are included, along with timing diagrams and reference data for connected storage modules.